The present invention relates to delay lock loops, and in particular to a delay lock loop with wide frequency range capability.
Delay lock loops are known in which a delayed clock signal is generated with a selected phase delay (e.g. 360xc2x0) from the original clock signal. The circuitry which acquires a xe2x80x9clockxe2x80x9d on the desired phase delay typically is designed to operate within a limited frequency range of perhaps an octave or less, and may not be capable of acquiring a lock on a clock signal outside this frequency range. Moreover, a step increase in clock frequency while a conventional delay lock loop is operating may result in the delay lock loop acquiring a false lock on the signal, or in other words locking on to a phase delay other than the desired phase delay. A false lock is particularly likely when the new clock frequency is an integer multiple of (e.g. two or three times) the original clock frequency. A step increase in clock frequency may also cause a conventional delay lock loop to enter a state of instability, which is defined as a state in which the delay lock loop oscillates between searching for a lock and reaching terminal delay limits. These limitations of conventional delay lock loops may limit the applications in which delay lock loops may be used, or may place burdensome design constraints on the circuits to be used with a delay lock loop.
Thus, a need has arisen for a delay lock loop that addresses the disadvantages and deficiencies of the prior art. Accordingly, a delay lock loop with wide frequency range capability is disclosed. In one embodiment, the delay lock loop circuit includes a delay block which receives the clock signal and delays the clock signal by a selected amount to generate the delayed clock signal. A phase detector receives-the clock signal and the delayed clock signal, compares the phases of the two signals and generates a phase comparison signal. A lock detector receives the clock signal and the delayed clock signal, compares the timing of the two signals and generates a potential lock indication signal, A controller receives the phase comparison signal and the potential lock indication signal and provides a delay control signal to the delay block to change the selected delay amount in response to the phase comparison signal. The controller interrupts the clock signal to the delay block for a selected interval in response to the potential lock indication signal, and generates a true lock indication signal in response to the potential lock indication signal after the interruption of the clock signal to the delay block.
A technical advantage of the present invention is that the delay lock loop circuit is capable of reliably and accurately handling an instantaneous change in the clock frequency.